SH7041A datasheet(552/923 Pages) RENESAS

552 / 923 page

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Communication Formats: Four formats are available. Parity-bit settings are ignored when the

multiprocessor format is selected. For details see table 14.8.

Clock: See the description in the asynchronous mode section.

Receiving

processor A

(ID = 01)

(ID = 02)

(ID = 03)

(ID = 04)

Receiving

processor B

Receiving

processor C

Serial communication line

H'01

H'AA

(MPB = 0)

(MPB = 1)

ID-transmit cycle:

receiving processor address

Serial

data

MPB:

Example:

Multiprocessor bit

Sending data H'AA to receiving processor A

Transmitting

processor

Receiving

processor D

Data-transmit cycle:

data sent to receiving

processor specified by ID

Figure 14.10 Communication among Processors Using Multiprocessor Format

Transmitting Multiprocessor Serial Data: Figure 14.11 shows a sample flowchart for

transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the

numbers in the flowchart):

1.SCI initialization: Set the TxD pin using the PFC.

2.SCI status check and transmit data write: Read the serial status register (SSR), check that the

TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT

(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.

3.Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it

reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC or the DTC is

started by a transmit-data-empty interrupt request (TxI) to write data in TDR, the TDRE bit is

checked and cleared automatically.

4.Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then

clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.

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