SH7041A datasheet(583/923 Pages) RENESAS

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• Bit 2—Simultaneous Sampling (DSMP): Enables or disables the simultaneous sampling of two

channels. See section 15.4.6, Simultaneous Sampling Operation, for details on simultaneous

sampling.

Set the DSMP bit only while conversion is halted.

Bit 2: DSMP

Description

Normal sampling operation (initial value)

Simultaneous sampling operation

• Bits 1–0—Buffer Enable 1, 0 (BUFE1, BUFE0): These bits select whether to use the

ADDRB–ADDRD as buffer registers.

Set the BUFE1 and BUFE0 bits only while conversion is halted.

Bit 1: BUFE1

Bit 0: BUFE0

Description

Normal operation (initial value)

ADDRA and ADDRB buffer operation: conversion result

→

ADDRA

→ ADDRB (ADDRB is the buffer register)

ADDRA and ADDRC, also ADDRB and ADDRD buffer

operation: conversion result 1

→ ADDRA → ADDRC,

conversion result 2

→ ADDRB → ADDRD (ADDRC and

ADDRD are buffer registers)

ADDRA–ADDRD buffer operation: conversion result

→

ADDRA

→ ADDRB → ADDRC → ADDRD (ADDRB–ADDRD

are buffer registers)

15.3

Bus Master Interface

The ADDRA–ADDRH are 16-bit registers with a 16-bit width data bus to the bus master. The bus

master can read from ADDRA–ADDRH in either word or byte units.

When an ADDR is read in word units, the ADDR contents are transferred to the bus master 16 bits

at a time. In byte unit reads, the contents of the most significant eight bits (AD9–AD2) of the

converted data (AD9–AD0) are transferred to the bus master.

Figures 15.2 and 15.3 shows an example of the ADDR read operation.

SH7041A Datasheet(PDF) 583 Page - Renesas Technology Corp