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SH7041A Datasheet(PDF) 586 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 586 Page - Renesas Technology Corp

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15.4
Operation
• The high speed A/D converter has 10-bit resolution.
• In addition to the four operating modes of select or group, and single or scan can be set in
combination with buffer operation and simultaneous sampling operation.
• Select mode uses one channel and group mode selects multiple channels.
• One start in the single mode performs conversions on all selected channels, and one start in the
scan mode performs repeated conversions until stopped by software.
• In buffer operation, the previous conversion result is saved in a buffer register at the end of a
conversion for the relevant channel.
• In simultaneous sampling operation, the analog input voltages of two channels are sampled
simultaneously then converted in order.
• Software, a timer conversion start trigger (MTU), or an ADTRG input can be selected as the
conversion start condition.
• High speed start mode or low power conversion mode can be selected for A/D conversion
using the PWR bit setting.
• When changing the operation mode or input channel, rewrite the ADCSR, ADCR while the
ADST bit is cleared to 0. After rewriting the ADCSR, ADCR, A/D conversion will be restarted
when the ADST bit is set to 1. Operation mode or input channel changes can be made
simultaneously with ADST bit setting. When stopping an A/D conversion before completion, 0
clear the ADST bit.
15.4.1
Select-Single Mode
Choose select-single mode when doing A/D conversions for one channel only.
When the ADST bit is set to 1, A/D conversion is started according to the designated conversion
start conditions. The ADST bit is held to 1 during the A/D conversion and is automatically cleared
to 0 upon completion.
The ADF flag is also set to 1 at the end of conversion. If the ADIE bit is set to 1 at this time, an
ADI interrupt request is generated. The ADF flag is cleared by reading the ADCSR, then writing a
0.
Figure 15.4 shows an example of operation in the select-single mode when AN1 is selected.



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