SH7041A datasheet(758/923 Pages) RENESAS

758 / 923 page

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22.8.3

Error Protection

In error protection, an error is detected when microcomputer runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

If the SH7051 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in

FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2

settings are retained, but program mode or erase mode is aborted at the point at which the error

occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, P2, E1, or E2

bit. However, PV1, PV2, EV1, and EV2 bit setting is enabled, and a transition can be made to

verify mode.

FLER bit setting conditions are as follows:

1. When flash memory is read during programming/erasing (including a vector read or instruction

fetch)

2. Immediately after exception handling (excluding a reset) during programming/erasing

3. When a SLEEP instruction (including software standby) is executed during

programming/erasing

4. When the bus is released during programming/erasing

Error protection is released only by a reset and in hardware standby mode.

Figure 22.15 shows the flash memory state transition diagram.

SH7041A Datasheet(PDF) 758 Page - Renesas Technology Corp