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STM32H750VB Datasheet(PDF) 190 Page - STMicroelectronics |
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STM32H750VB Datasheet(HTML) 190 Page - STMicroelectronics |
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190 / 335 page  Electrical characteristics (rev Y) STM32H750VB STM32H750ZB STM32H750IB STM32H750XB 190/334 DS12556 Rev 5 Figure 50. SAI master timing waveforms Figure 51. SAI slave timing waveforms MDIO characteristics The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at least 1.5 times the MDC frequency: FPCLK2 ≥ 1.5 * FMDC. Table 107. MDIO Slave timing parameters Symbol Parameter Min Typ Max Unit FsDC Management data clock - - 40 MHz td(MDIO) Management data input/output output valid time 78 20 ns tsu(MDIO) Management data input/output setup time 4- - th(MDIO) Management data input/output hold time 1- - MS32771V1 SAI_SCK_X SAI_FS_X (output) 1/fSCK SAI_SD_X (transmit) tv(FS) Slot n SAI_SD_X (receive) th(FS) Slot n+2 tv(SD_MT) th(SD_MT) Slot n tsu(SD_MR) th(SD_MR) MS32772V1 SAI_SCK_X SAI_FS_X (input) SAI_SD_X (transmit) tsu(FS) Slot n SAI_SD_X (receive) tw(CKH_X) th(FS) Slot n+2 tv(SD_ST) th(SD_ST) Slot n tsu(SD_SR) tw(CKL_X) th(SD_SR) 1/fSCK |
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