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STM32H750VB Datasheet(PDF) 187 Page - STMicroelectronics |
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STM32H750VB Datasheet(HTML) 187 Page - STMicroelectronics |
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187 / 335 page ![]() DS12556 Rev 5 187/334 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Electrical characteristics (rev Y) 311 I2S interface characteristics Unless otherwise specified, the parameters given in Table 105 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.5VDD I/O compensation cell enabled Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 105. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256x8K 256FS MHz fCK I2S clock frequency Master data - 64FS MHz Slave data - 64FS tv(WS) WS valid time Master mode - 3.5 ns th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 1 - tsu(SD_MR) Data input setup time Master receiver 1 - tsu(SD_SR) Slave receiver 1 - th(SD_MR) Data input hold time Master receiver 4 - th(SD_SR) Slave receiver 2 - tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 20 tv(SD_MT) Master transmitter (after enable edge) - 3 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 9 - th(SD_MT) Master transmitter (after enable edge) 0 - 1. Guaranteed by characterization results. |
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