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STM32H750VB Datasheet(PDF) 205 Page - STMicroelectronics |
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STM32H750VB Datasheet(HTML) 205 Page - STMicroelectronics |
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205 / 335 page  DS12556 Rev 5 205/334 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Electrical characteristics (rev V) 311 fCPU Arm® Cortex®-M7 clock frequency VOS3 - - 200 MHz VOS2 - - 300 VOS1 - - 400 VOS0 - - 480(5) fHCLK AHB clock frequency VOS3 - - 100 VOS2 - - 150 VOS1 - - 200 VOS0 - - 240(5) fPCLK APB clock frequency VOS3 - - 50(6) VOS2 - - 75 VOS1 - - 100 VOS0 - - 120(5) TA Ambient temperature for the suffix 6 version Maximum power dissipation –40 85 °C Low-power dissipation(7) –40 105 TJ Junction temperature range Suffix 6 version –40 125 °C 1. When RESET is released functionality is guaranteed down to VBOR0 min 2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must be disabled. 4. VOS0 is available only when the LDO regulator is ON. 5. TJmax = 105 °C. 6. Maximum APB clock frequency when at least one peripheral is enabled. 7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.6: Thermal characteristics). Table 120. General operating conditions (continued) Symbol Parameter Operating conditions Min Typ Max Unit Table 121. Supply voltage and maximum frequency configuration Power scale VCORE source Max TJ (°C) Max frequency (MHz) Min VDD (V) VOS0 LDO 105 480 1.7 VOS1 LDO 125 400 1.62 VOS2 LDO 125 300 1.62 VOS3 LDO 125 200 1.62 SVOS4 LDO 105 N/A 1.62 SVOS5 LDO 105 N/A 1.62 |
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