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STM32H750VB Datasheet(PDF) 334 Page - STMicroelectronics

Part # STM32H750VB
Description  32-bit Arm® Cortex®-M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto
PDF  335 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H750VB Datasheet(HTML) 334 Page - STMicroelectronics

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DS12556 Rev 5
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Revision history
333
24-Apr-2019
4
Updated Figure 1: STM32H750xB block diagram
Updated Table 7: STM32H750xB pin/ball definition.
Updated Table 8 to Table 18 (alternate functions).
Updated Table 37: Peripheral current consumption in Run mode.
Updated Table 135: Peripheral current consumption in Run mode.
Updated Table 182: ADC characteristics.
Updated Table 183: Minimum sampling time vs RAIN.
Updated Table 184: ADC accuracy.
Added device marking examples for all packages in Section 8: Package information
22-Nov-2019
5
Added LQFP144 package together with STM32H750ZB part number, and LQFP176
package.
In Table 1: STM32H750xB features and peripheral counts, split number of ADC
channels into Direct, Fast and Slow channels; and added number of wakeup and tamper
pins.
Moved LSI from Backup to VDD domain in Figure 11 and Figure 64.
Updated capacitor value for 1.62 V<DD<1.8 V and FMC_CLK =100 MHz in Section :
SDRAM waveforms and timings.
Updated Section 6.2 and Section 7.2 introduction to device mission profile.
Power dissipation (PD) removed from Tables General operating conditions since this
parameter is redundant with
JA thermal resistance.
Updated maximum frequency for condition “All peripherals disabled and VOS2”
Table 128: Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory, cache ON, LDO regulator ON
Updated condition related to
frcc_c_ck in Section : On-chip peripheral current
consumption.
Updated Table 179: QUADSPI characteristics in SDR mode, Figure 35: Quad-SPI
timing diagram - DDR mode and Figure 87: Quad-SPI timing diagram - DDR mode.
Updated fDFSDMCLK maximum value in Table 98: DFSDM measured timing - 1.62-3.6 V
and Table 196: DFSDM measured timing - 1.62-3.6 V.
Updated notes 4. and 5. in Table 183: Minimum sampling time vs RAIN.
Updated Figure 128: TFBGA240+25 package outline.
Added note related to the availability of tape and reel packing in Section 9: Ordering
information.
Table 223. Document revision history
Date
Revision
Changes



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