AD4116BCPZ datasheet(4/59 Pages) AD

4 / 59 page

AD4116

Data Sheet

Rev. 0 | Page 4 of 59

SPECIFICATIONS

Single-supply: AVDD = 4.5 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, and VBIAS− = 0 V, unless otherwise noted.

Split-supply: AVDD = 2.5 V, IOVDD = 2 V to 3.6 V, AVSS = −2.5 V, DGND = 0 V, and VBIAS− = AVSS, unless otherwise noted.

Internal reference, internal master clock (MCLK) = 4 MHz, and TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

VOLTAGE INPUTS (VINx)

Differential Input Voltage Range1

Specified performance

−10

+10

Functional

−VREF × 10

+VREF × 10

Absolute (Pin) Input Voltage

−20

+20

Input Impedance

MΩ

Offset Error2

25°C, 192.5 µs settling

±3

Offset Drift

192.5 µs settling

±30

µV/°C

Gain Error

25°C, 192.5 µs settling

±0.05

% of FS

Gain Drift

192.5 µs settling

±5

ppm/°C

Integral Nonlinearity (INL)

192.5 µs settling

±0.02

% of FSR

Total Unadjusted Error (TUE)3

96.5 µs settling4

25°C, internal reference

±0.1

% of FSR

−40°C to +105°C, internal reference

±0.2

% of FSR

192.5 µs settling

25°C, internal reference

±0.1

% of FSR

−40°C to +105°C, internal reference

±0.15

% of FSR

Power Supply Rejection

AVDD for input voltage (VIN) = 1 V

Common-Mode Rejection

VIN = 1 V

At DC

At 50 Hz, 60 Hz

20 Hz output data rate (post filter),

50 Hz ± 1 Hz and 60 Hz ± 1 Hz

120

Normal Mode Rejection4

50 Hz ± 1 Hz and 60 Hz ± 1 Hz

Internal clock, 20 SPS ODR (post filter)

External clock, 20 SPS ODR (post filter)

Resolution

See Table 7 and Table 8

Noise

See Table 7 and Table 8

LOW LEVEL INPUTS (ADCINx)

Differential Input Voltage Range

Reference voltage (VREF) = (REF+) − (REF−)

±VREF

Absolute (Pin) Input Voltage

Input Buffers Disabled

AVSS − 0.05

AVDD + 0.05

Input Buffers Enabled

AVSS

AVDD

Analog Input Current

Input Buffers Disabled

µA/V

Input Buffers Enabled

2.7

Offset Error2

±60

µV

Offset Drift

±300

nV/°C

Gain Error

Internal full-scale calibration5, 25°C

±0.01

% of FS

Gain Drift

±5

ppm/°C

Integral Nonlinearity (INL)

±15

ppm of FSR

Total Unadjusted Error (TUE)3, 4

Internal calibration

25°C, internal reference

0.03

% of FSR

−40°C to +105°C, internal reference

0.06

% of FSR

Power Supply Rejection

AVDD for VIN = 1 V

Common-Mode Rejection

VIN = 0.1 V

At DC

At 50 Hz, 60 Hz

20 Hz output data rate (post filter),

50 Hz ± 1 Hz and 60 Hz ± 1 Hz

120

AD4116BCPZ Datasheet(PDF) 4 Page - Analog Devices

AD4116BCPZ Datasheet(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL