AD4116BCPZ datasheet(39/59 Pages) AD

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Data Sheet

AD4116

Rev. 0 | Page 39 of 59

STANDBY AND POWER-DOWN MODES

In standby mode, most blocks are powered down. The LDO

regulators remain active so that the registers maintain their

contents. The crystal oscillator remains active if selected. To

power down the clock in standby mode, set the CLOCKSEL bits

in the ADC mode register to 00 (internal oscillator mode).

In power-down mode, all blocks are powered down, including

the LDO regulators. All registers lose their contents, and the GPIO

outputs are placed in three-state. To prevent accidental entry to

power-down mode, the ADC must first be placed in standby

mode. Exiting power-down mode requires 64 SCLKs with CS =

0 and DIN = 1, that is, a serial interface reset. A delay of 500 µs is

recommended before issuing a subsequent serial interface

command to allow the LDO regulator to power up.

CALIBRATION

The AD4116 allows a 2-point calibration to be performed to

eliminate any offset and gain errors. The following four calibration

modes are used to eliminate these offset and gain errors on a per

setup basis:

•

Internal zero-scale calibration mode

•

Internal full-scale calibration mode

•

System zero-scale calibration mode

•

System full-scale calibration mode

Only one channel can be active during calibration. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

The default value of the offset register is 0x800000, and the

default value of the gain register is 0x5XXXX0. The following

equations show the calculations that are used. In unipolar mode,

the ideal relationship (that is, not taking into account the ADC

gain error and offset error) is as follows:

For the voltage inputs,

Data = ((0.075 × VIN/VREF) × 223 − (Offset − 0x800000)) ×

(Gain/0x400000) × 2

For the low level inputs,

Data = ((0.75 × VADCIN/VREF) × 223 − (Offset − 0x800000)) ×

(Gain/0x400000) × 2

In bipolar mode, the ideal relationship (that is, not taking into

account the ADC gain error and offset error) is as follows:

For the voltage inputs,

Data = ((0.075 × VIN/VREF) × 223 − (Offset − 0x800000)) ×

(Gain/0x400000) + 0x800000

For the low level inputs,

Data = ((0.75 × VADCIN/VREF) × 223 − (Offset − 0x800000)) ×

(Gain/0x400000) + 0x800000

To start a calibration, write the relevant value to the mode bits

in the ADC mode register. The DOUT/RDY pin and the RDY bit

in the status register go high when the calibration initiates. When

the calibration is complete, the contents of the corresponding

offset or gain register are updated, the RDY bit in the status

and the AD4116 reverts to standby mode.

During an internal offset calibration, both modulator inputs are

connected internally to the selected negative analog input pin.

Therefore, it is necessary to ensure that the voltage on the selected

negative analog input pin does not exceed the allowed limits

and is free from excessive noise and interference. A full-scale,

low level, input voltage automatically connects to the ADC

input to perform an internal full-scale calibration.

However, for system calibrations, the system zero-scale (offset)

and system full-scale (gain) voltages must be applied to the

input pins before initiating the calibration modes. As a result,

errors external to the AD4116 are removed.

The calibration range of the ADC gain for a system full-scale

calibration on a voltage input is from 3.75 × VREF to 10.5 × VREF.

However, if 10.5 × VREF is greater than the absolute input voltage

specification for the applied AVDD, use the specification as the

upper limit instead of 10.5 × VREF (see the Specifications section).

The calibration range of the ADC gain for a system full-scale

calibration on a low level input is from 0.4 × VREF to 1.05 × VREF.

An internal zero-scale calibration only removes the offset error

of the ADC core. It does not remove error from the resistive

front end. A system zero-scale calibration reduces the offset

error to the order of the noise on that channel.

From an operational point of view, treat a calibration like

another ADC conversion. An offset calibration, if required,

must always be performed before a full-scale calibration. Set the

system software to monitor the RDY bit in the status register or

the RDY output to determine the end of a calibration via a

polling sequence or an interrupt driven routine. All calibrations

require a time equal to the settling time of the selected filter and

output data rate to be completed.

Any calibration can be performed at any output data rate.

Using lower output data rates results in better calibration

accuracy and is accurate for all output data rates. A new offset

calibration is required for a given channel if the reference

source for that channel is changed.

The AD4116 provides the user with access to the on-chip

calibration registers, allowing the microprocessor to read the

calibration coefficients of the device and to write its own

calibration coefficients. A read or write of the offset and gain

registers can be performed at any time except during an internal or

self calibration.

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