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db12348e_V3.11_preliminary_2017-07-06

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AS89010

V3.11

5.5 Conversion Time Measurement

In case of SYND measurement mode the conversion time is fully controlled by the external signal at pin

SYN. The relative deviation of this time to the internal clock frequency15 can produce some deviations in

the conversion output. However, this time can be internally measured in time units of system clock

(typically 1024 MHz) up to 20 bit word. It gives the opportunity to calculate more precisely measured input

currents. That could increase the accuracy for the converter.

Even further, the measured result can be compensated for any deviation which can occur in the clock

frequency due to temperature or supply voltage variations.

The time measurement can be enabled by setting the ENTM bit of register CREGH (Table 11). The result is

stored into the output register OUTINT (Table 15) after a conversion has been made, synchronous with the

storing of the A/D conversion data. The stored value follows the relation:

CLK

TINT

OUTINT





(8)

The register OUTINT is only valid if this mode has been activated.

5.6 I²C Communication

The two wire serial interface is compatible to the fast mode I²C protocol and timing16. The SDA wire carries

the data while the SCL wire synchronizes the transmitter and receiver. The device that initiates a data

transfer is called a master and the responding device is called a slave. A device that sends data to the bus

is called transmitter and a device receiving the data is called receiver.

The AS89010 can operate only as slave with unique slave address 11101‘A1 A0’ (7 address bit’s plus

read/write bit, see Figure 11), with the two lower bits defined by the input pins A1, A0. Each data transfer

begins with a start (S) condition, defined by a high to low transition of SDA while SCL is high. The transfer

terminates by a stop (P) condition, defined by a low to high transition of SDA while SCL is high. A repeated

start condition (Sr) can be generated instead of a stop condition, if the transfer should be continued with

the new data packet.

The start and repeated start condition are functionally equivalent. The data transfer consists of 8 bit long

data. Each byte has to be followed by an acknowledge bit (A) (see Figure 11). The bits arrive with the MSB

first. The acknowledge signal shall be pulled low by the receiver during the high period of the 9th clock

pulse, while transmitter releases the SDA line. When SDA stays high during this clock pulse then this is

defined as the not acknowledge signal (NA). After the not acknowledge signal, the master can either

generate a stop or repeated start condition, depends on whether the master wants to abort or start a new

transfer. The AS89010 generates a not acknowledge only in case when received data are not understood.

The data transfer is implemented as shown in Figure 11.

A master generates the start condition and sends a 7 bit long slave address followed by the 8th bit which

is a data direction bit (h). With the data direction bit set to ‘1’ a master indicates a request for data read

with a ‘0’ a transmission is indicated. A data transfer terminates by a stop condition, but the master can

also generate a repeated start condition instead of stop condition if the communication should be continued.

The sequences for a read and write data transfer are shown in Figure 12.

15 It depends on technology parameters in manufacturing. So variations and tolerances from one IC to another can occur.

16 The requirements for bus termination using standard Pull-Up’s according I²C should be considered. It concerns especially noise envi-

ronments and EMC in PCB design.

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