SPC572L64F2 datasheet(60/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC572Lx

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DocID027866 Rev 5

tSM2NM_TX

Transmitter startup time (sleep

mode to normal mode)(7)

Not applicable to the

MSC/DSPI LVDS

pad

—0.2

0.5

µs

tPD2NM_RX

Receiver startup time (power down

to normal mode)(8)

—

tPD2SM_RX

Receiver startup time (power down

to sleep mode)(9)

Not applicable to the

MSC/DSPI LVDS

pad

—20

ILVDS_BIAS

LVDS bias current consumption

Tx or Rx enabled

—

0.95

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Transmission line characteristic

impedance

—

47.5

52.5

ZDIFF

Transmission line differential

impedance

—

100

105

RECEIVER

VICOM

Common mode voltage

—

0.15(10)

—1.6(11)

ΔVI|

Differential input voltage(12)

—

100

—

VHYS

Input hysteresis

—

RIN

Terminating resistance

VDD_HV_IO =

5.0 V ± 10%

125

150

DVDD_HV_IO =

3.3 V ± 10%

115

150

CIN

Differential input capacitance(13)

——

3.5

6.0

ILVDS_RX

Receiver DC current consumption Enabled

—

0.5

1. The LVDS pad startup and receiver electrical characteristics in this table apply to the LFAST LVDS pad, and the MSC/DSPI

LVDS pad except where noted in the conditions.

2. All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS

control registers (LCR) of the LFAST and module. The value of the LCR bits for the LFAST/HSD modules don’t take effect

until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for MSC/DSPI LVDS are

defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding SIUL2 MSCR ODC field.

4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter

electrical characteristic tables.

5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being

enabled.

6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock

periods.

7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode.

8. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods.

9. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode.

10. Absolute min = 0.15 V – (285 mV/2) = 0 V

11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

Table 28. LVDS pad startup and receiver electrical characteristics(1)(2) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

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