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SPC572L64F2 Datasheet(PDF) 88 Page - STMicroelectronics |
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SPC572L64F2 Datasheet(HTML) 88 Page - STMicroelectronics |
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88 / 112 page ![]() Electrical characteristics SPC572Lx 88/112 DocID027866 Rev 5 Figure 35. RMII serial management channel timing diagram 3.17.3.2 RMII receive signal timing (RXD[1:0], CRS_DV) The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency. M11 MDC (output) MDIO (output) M12 M13 MDIO (input) M10 M14 M15 Table 47. RMII receive signal timing(1) Symbol C Characteristic Value Unit Min Max R1 CC D RXD[1:0], CRS_DV to REF_CLK setup 4 — ns R2 CC D REF_CLK to RXD[1:0], CRS_DV hold 2 — ns R3 CC D REF_CLK pulse width high 35% 65% REF_CLK period R4 CC D REF_CLK pulse width low 35% 65% REF_CLK period 1. All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V. |
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