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STM32WB15CC Datasheet(PDF) 112 Page - STMicroelectronics

Part # STM32WB15CC
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution
PDF  127 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WB15CC Datasheet(HTML) 112 Page - STMicroelectronics

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Electrical characteristics
STM32WB15CC
112/127
DS13258 Rev 4
This limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:
tr(SDA/SCL) = 0.8473 x Rp x Cload
Rp(min) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up. Refer to Section 6.3.16 for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 79 for its characteristics.
SPI characteristics
Unless otherwise specified, the parameters given in Table 80 are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 21: General operating conditions.
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are set at CMOS levels: 0.5 x VDD
Refer to Section 6.3.16 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).
Table 79. I2C analog filter characteristics(1)
1. Specified by design, not tested in production.
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes that
are suppressed by the analog filter
50(2)
2. Spikes with widths below tAF(min) are filtered.
100(3)
3. Spikes with widths above tAF(max) are not filtered
ns
Table 80. SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
1.71 < VDD < 3.6 V
--
32
MHz
Slave receiver mode
1.71 < VDD < 3.6 V
32
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V
32(2)
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V
24(2)
tsu(NSS) NSS setup time
Slave mode, SPI prescaler = 2
4xTPCLK
--
-
th(NSS) NSS hold time
Slave mode, SPI prescaler = 2
2xTPCLK
--
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
TPCLK - 1.5
TPCLK
TPCLK + 1



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