STM32WB50CG datasheet(49/119 Pages) STMICROELECTRONICS

49 / 119 page

DS13047 Rev 5

49/119

STM32WB50CG STM32WB30CE

Pinouts and pin description

PB7

I/O FT_fa

LPTIM1_IN2, TIM1_BKIN, I2C1_SDA,

USART1_RX, TIM17_CH1N,

CM4_EVENTOUT

PVD_IN

VDD

1. PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the

use of the PC14 and PC15 GPIOs in output mode is limited:



- the speed must not exceed 2 MHz with a maximum load of 30 pF



- these GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the

RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup

domain and RTC register descriptions in the reference manual RM0471, available on www.st.com.

3. The clock on LSCO is available in Run, Stop, and on PA2 in Standby and Shutdown modes.

4. On UFQFPN48 VDDA is connected to VREF+.

5. RF pin, use the nominal PCB layout.

6. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165).

7. Reserved for production, must be kept unconnected.

8. High frequency (above 32 KHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0

and 1) during RF operation.

9. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and

PB4 pins and the internal pull-down on PA14 pin are activated.

Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions (continued)

Pin (UFQFPN48)

Alternate functions

Additional functions

Name (function

after reset)

STM32WB50CG Datasheet(PDF) 49 Page - STMicroelectronics