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ST25R3918 Datasheet(PDF) 134 Page - STMicroelectronics |
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ST25R3918 Datasheet(HTML) 134 Page - STMicroelectronics |
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134 / 141 page  Electrical characteristics ST25R3918 134/141 DS13490 Rev 2 Table 122. 1 MHz AC characteristics(1)(2) 1. Conditions in addition to those specified in Table 116 and Table 117. 2. Evaluated by characterization, not tested in production. Symbol Alt. Parameter Min Max Unit fC fSCL Clock frequency - 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 500 - tQL1QL2 tF SDA (out) fall time - 120 tDXCH tSU:DAT Data in set up time 50 - tCLDXXtHD:DAT Data in hold time 0 - tCLQX tDH Data out hold time 50 - tCLQV tAA Clock low to next data valid (access time) - 450 tCHDL tSU:STA Start condition setup time 250 - tDLCL tHD:STA Start condition hold time 250 - tCHDH tSU:STO Stop condition set up time 250 - tDHDL tBUF Time between Stop condition and next Start condition 500 - tNS - Pulse width ignored (input filter on SCL and SDA), single glitch -40 Table 123. 3.4 MHz AC characteristics(1)(2)(3) Symbol Alt. Parameter Min Max Unit fC fSCL Clock frequency - 3.4 MHz tCHCL tHIGH Clock pulse width high 80 - ns tCLCH tLOW Clock pulse width low 160 - tQL1QL2 tF SDA (out) fall time (10-100 pF) - 41 tDXCH tSU:DAT Data in set up time 25 - tCLDXXtHD:DAT Data in hold time 0 - tCLQX tDH Data out hold time 20 - tCLQV tAA Clock low to next data valid - 150 tCHDL tSU:STA Start condition setup time 160 - tDLCL tHD:STA Start condition hold time 160 - tCHDH tSU:STO Stop condition set up time 160 - tNS - Pulse width ignored (input filter on SCL and SDA), single glitch -10 1. Conditions in addition to those specified in Table 116 and Table 117. 2. Evaluated by characterization, not tested in production. 3. VDD_IO supply must not exceed VDD. |
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