ADMV8526ACCZ-R7 datasheet(14/31 Pages) AD

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Data Sheet

ADMV8526

THEORY OF OPERATION

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SPI FAST LATCH MODE

The ADMV8526 has a 32 state LUT and an internal state machine

that is useful for quickly changing filter states in SPI fast latch

mode. When the SFL pin is high, SPI fast latch mode enables, and

the internal state machine sequences on each rising edge of the CS

pin.

The LUT has 32 groupings, LUT0 through LUT31, in Register

0x100 through Register 0x15F. Each grouping consists of the same

type of parameters as those for SPI write mode.

The functionality of the internal state machine is such that on each

rising edge of the CS pin, the internal state machine sequences a

pointer based on the programmed direction.

The internal state machine has the following parameters:

►

FAST_LATCH_STOP (Register 0x011)

►

FAST_LATCH_START (Register 0x012)

►

FAST_LATCH_DIRECTION (Register 0x013)

►

FAST_LATCH_STATE (Register 0x014)

The FAST_LATCH_STATE is the next LUT grouping that is selected

on the next rising edge of the CS pin. The FAST_LATCH_ STATE is

considered the internal pointer location.

When the FAST_LATCH_DIRECTION bit is set to 0, the sequenc-

ing direction is incremental. When the FAST_LATCH_ DIRECTION

bit is set to 1, the sequencing direction is decremental.

The FAST_LATCH_START and FAST_LATCH_STOP bits are used

to set the start and stop location, respectively. For incremental di-

rection, the internal state machine sequences from the start location

to the stop location and then rolls over to the start location. For the

decremental direction, the sequence is from the stop location to the

start location and then rolls over to the stop location.

The FAST_LATCH_STATE internal pointer is set to the values

stored in FAST_LATCH_START for the incremental direction. For

the decremental direction, the internal pointer is set to the values

stored in FAST_LATCH_STOP. For this transaction to occur, one

rising edge of the CS pin is necessary. By nature, this occurs

during a SPI transaction in SPI write mode. However, when exiting

SPI fast latch mode (SFL pin brought low), be sure to toggle the

CS pin low then high or perform a SPI transaction so that the

FAST_LATCH_STATE refreshes to either the start or stop location

accordingly.

CHIP RESET

Two methods are available to reset the ADMV8526 registers to their

default power-on state, a hard reset and a soft reset. The hard reset

uses the RST pin, and the soft reset utilizes Register 0x000.

To perform a hard reset, momentarily bring the RST pin low and

then high. See Figure 2 for the minimum required duration time for

the RST pin to be low.

To perform a soft reset, set Register 0x000 to 0x81. This action sets

the SOFTRESET and SOFTRESET_ bits high to initiate the reset.

The SOFTRESET and SOFTRESET_ bits are self resetting once

the reset operation completes.

Regardless of the reset method used, it is recommended to perform

the following after the chip resets:

►

Set Register 0x000 to 0x3C to enable the SDO pin and allow SPI

streaming with Endian ascending order.

►

Read back all registers on the chip.

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