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CYT4BFCCJS Datasheet(PDF) 44 Page - Infineon Technologies AG |
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CYT4BFCCJS Datasheet(HTML) 44 Page - Infineon Technologies AG |
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44 / 217 page ![]() 12 Power pin assignments Table 12-1 Power pin assignments Pin Name Package Remarks 320-BGA 272-BGA 176-TEQFP VDDD F8, F9, H15, J15, K15, L15, M15, N15, R12, R13 F8, H13, J13, K13, L13, N11 176, 153, 132, 110, 43, 22 Main digital supply VSSD A1, A20, C3, C10, C18, H9, H10, H11, H12, H13, J9, J10, J11, J12, J13, J18, K9, K10, K11, K12, K13, K18, L9, L10, L11, L12, L13, M9, M10, M11, M12, M13, N12, V3, V4, V15, Y1, Y20 A1, A18, D9, G7, G12, H9, H10, H11, J9, J10, J11, J15, K9, K10, K11, M7, M12, R5, R14, V1, V18 155, 154, 133, 114, 89, 45, 23, 1 Main digital ground VSSD_1 N13 L11 NA Digital Ground VSSD_2 L20, P20 L18, P18 NA Noise guard for ECO inputs VDDIO_1 F10, F11, F12, F13 F9, F10, F11 44 I/O supply (except analog I/Os on VDDA) VDDIO_2 R8 N8 88 I/O supply (except analog I/Os on VDDA) VDDIO_3 H6, J6, K6, L6 H6, J6 NA I/O supply for high speed domain#0 (HSIO_STD), P24, P25 VDDIO_4 R9, R10, R11 N9, N10 NA I/O supply for high speed domain#1 (HSIO_STD), P26, P27, P33, P34 VSSIO_3 H8, J8, K8, L8 H8, J8 NA HSIO ground VSSIO_4 N9, N10, N11 L9, L10 NA HSIO ground VCCD[24] F6, F15, R6, R15 F6, F13, N6, N13 46, 47, 111, 112, 113, 156 Main regulated supply. Driven by LDO regulator (either internal LDO or external LDO/PMIC) VREFH M6 K6 79 High reference voltage for SAR ADCs VREFL M8 K8 76 Low reference voltage for SAR ADCs VDDA N6 L6 78 Main analog supply for SAR ADCs VSSA N8 L8 77 Main analog ground XRES_L K20 K18 152 Active LOW external reset input DRV_VOUT J20 J18 160 Dedicated external supply control pin Note 24.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 26-2) |
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