CYT4BFCCJS datasheet(12/217 Pages) INFINEON

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Datasheet

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002-21617 Rev. *J

2022-02-18

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.1

CPU subsystem

3.1.1

CPU

The CYT4BF CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and two 32-bit Arm® Cortex®-M7

CPUs, each with MPU, single/double-precision FPU, and 16-KB data and instruction caches. This subsystem also

includes P-/M-DMA controllers, a cryptographic accelerator, 8384 KB of code-flash, 256 KB of work-flash, 1024 KB

of SRAM, and 64 KB of ROM.

The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following

completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,

SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by

an inter-processor communication (IPC) mechanism using hardware semaphores.

Each Cortex-M7 CPU has 16 KB of instruction and 16 KB of data TCM with programmable read wait states. Each

TCM is clocked by the associated Cortex-M7 CPU clock.

3.1.2

DMA controllers

CYT4BF has three DMA controllers: P-DMA0 with 16 general purpose and 127 dedicated channels, P-DMA1 with 8

general purpose and 57 dedicated channels, and M-DMA0 with eight channels. P-DMA is used for

peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of

channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.

General purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables

demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)

to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high

memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each

channel. They support independent accesses to peripherals using the AHB multi-layer bus.

3.1.3

Flash

CYT4BF has 8384 KB (8128 KB with a 32-KB sector size, and 256 KB with an 8-KB sector size) of code-flash with an

additional work-flash of 256 KB (192 KB with a 2-KB sector size, and 64 KB with a 128-B sector size). Work-flash is

optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)

operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support

dual-bank operation for over-the-air (OTA) programming.

3.1.4

SRAM

CYT4BF has 1024 KB of SRAM with three independent controllers. SRAM0 provides DeepSleep retention in 32-KB

increments while SRAM1/2 are selectable between fully retained and not retained.

3.1.5

ROM

CYT4BF has 64 KB of ROM that contains boot and configuration routines. This ROM enables secure boot and

authentication of user flash to guarantee a secure system.

3.1.6

Cryptography accelerator for security

The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy

check, pseudo random number generation, true random number generation, galois/counter mode, and a vector

unit to support asymmetric key cryptography such as RSA and ECC.

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