ADGM1304JCPZ-R2 datasheet(24/34 Pages) AD

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ADGM1304

Data Sheet

Rev. G | Page 24 of 34

SPI DIGITAL INTERFACE

The ADGM1304 can be controlled via an SPI digital interface

when Pin 6 (PIN/SPI) is high. The SPI is compatible with SPI

Mode 0 (clock polarity (CPOL) = 0, clock phase (CPHA) = 0) and

Mode 3 (CPOL = 1, CPHA = 1) and it operates with SCLK

frequencies up to 10 MHz. When the SPI is active, the default

mode is addressable, in which, the device registers are accessed by a

16-bit SPI command that is bound by the state of the CS pin.

The ADGM1304 can also operate in daisy-chain mode.

The SPI interface pins of the ADGM1304 are CS, SCLK, SDI, and

SDO. Hold CS low when using the SPI interface. The data on SDI

is captured on the rising edge of SCLK and data is propagated out

on SDO on the falling edge of SCLK. SDO has push-pull output

driver architecture that does not require pull-up resistors.

Addressable Mode

Addressable mode is the default mode for the ADGM1304 on

power up. A single SPI frame in addressable mode is bounded

by a CS falling edge and the succeedingCS rising edge. It

comprises 16 SCLK cycles. The timing diagram for addressable

mode, in SPI Mode 0, is shown in Figure 50.

The first SDI bit indicates if the SPI command is a read or write

command. The next seven bits determine the target register

address. The remaining eight bits provide the data to the

addressed register. The last eight bits are ignored during a read

command, during which time the SDO propagates out the data

contained in the addressed register.

In Mode 0, during any SPI command, SDO sends out eight

alignment bits on the CS falling edge and the first seven SCLK

falling edges (in Mode 3, the first SCLK falling edge is ignored

as shown in Figure 50). The alignment bits observed at SDO are

0x25.

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from the target register

propagates out on the SDO pin from the eighth to the 15th SCLK

falling edge during SPI reads. A register write occurs on the 16th

SCLK rising edge during SPI writes.

SDO

R/W

SDI

SCLK

Figure 49. Addressable Mode Timing Diagram (Mode 0)

SDO

R/W

SDI

SCLK

Figure 50. Addressable Mode Timing Diagram (Mode 3)

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