ADGM1304JCPZ-R2 datasheet(7/34 Pages) AD

Part #	ADGM1304JCPZ-R2

Description	0 Hz/dc to 14 GHz, Single-Pole, Four-Throw MEMS Switch with Integrated Driver

PDF	34 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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7 / 34 page

Data Sheet

ADGM1304

Rev. G | Page 7 of 34

TIMING CHARACTERISTICS

VDD = 3.0 V to 3.6 V, AGND = 0 V, RFGND = 0 V, all specifications TMIN to TMAX = 0°C to 85°C, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Conditions/Comments

100

ns min

Serial clock (SCLK) period

ns min

SCLK high pulse width

ns min

SCLK low pulse width

ns min

Chip select (CS) falling edge to SCLK active edge

ns min

Data setup time

ns min

Data hold time

ns min

SCLK active edge to CS rising edge

ns max

CS falling edge to SDO data available

t91

ns max

SCLK falling edge to SDO data available

t10

ns max

CS rising edge to SDO returns to high impedance

t11

100

ns min

CS high time between SPI commands

t12

ns min

SCLK edge rejection to chip select (CS) falling edge

t13

ns min

CS rising edge to SCLK edge rejection

Measured with a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.

t10

R/W

SCLK

SDI

SDO

Figure 2. Addressable Mode Timing Diagram

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