PIC18F1230-ESLASHMLQTP datasheet(80/312 Pages) MICROCHIP

80 / 312 page

PIC18F1230/1330

DS39758B-page 78

Advance Information

7.7

Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in

Configuration

Words.

External

read

and

write

operations are disabled if either of these mechanisms

are enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 19.0

“Special Features of the CPU” for additional

information.

7.8

Using the Data EEPROM

The

data EEPROM

high-endurance,

byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). Frequently changing values will typically be

updated more often than specification D124 or D124A.

If this is not the case, an array refresh must be

performed. For this reason, variables that change

infrequently (such as constants, IDs, calibration, etc.)

should be stored in Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE

TABLE 7-1:

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Note:

If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification D124 or D124A.

CLRF

EEADR

; Start at address 0

BCF

EECON1, CFGS

; Set for memory

BCF

EECON1, EEPGD

; Set for Data EEPROM

BCF

INTCON, GIE

; Disable interrupts

BSF

EECON1, WREN

; Enable writes

LOOP

; Loop to refresh array

BSF

EECON1, RD

; Read current address

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

MOVLW

0AAh

;

MOVWF

EECON2

; Write 0AAh

BSF

EECON1, WR

; Set WR bit to begin write

BTFSC

EECON1, WR

; Wait for write to complete

BRA

$-2

INCFSZ

EEADR, F

; Increment address

BRA

Loop

; Not zero, do it again

BCF

EECON1, WREN

; Disable writes

BSF

INTCON, GIE

; Enable interrupts

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values on

page

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

EEADR

EEPROM Address Register

EEDATA EEPROM Data Register

EECON2 EEPROM Control Register 2 (not a physical register)

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

IPR2

OSCFIP

—

EEIP

—

LVDIP

—

—43

PIR2

OSCFIF

—

EEIF

—

LVDIF

—

—43

PIE2

OSCFIE

—

EEIE

—

LVDIE

—

—43

Legend:

= unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/

EEPROM access.

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