L6711

14/38

Figure 6. Current Reading Connections selectable through CS_SEL pin.

5.1

LOW SIDE Current Reading

Leaving CS_SEL pin OPEN, the current flowing trough each phase is read using the voltage drop across

rent. The transconductance ratio is issued by the external resistor Rg placed outside the chip between

CSx- and CSx+ pins toward the reading points (see Figure 7 right). The proprietary current sense circuit

side mosfet conduction time (OFF Time, see Figure 7 left) and holds the tracked information during the

rest of the period.

This device sources a constant 50

µA current from the CSx+ pin: the current reading circuitry uses this pin

as a reference and the reaction keeps the CSx- pin to this voltage during the reading time (an internal

clamp keeps CSx+ and CSx- at the same voltage sinking from the CSx- pin the necessary current during

rating overcome on CSx- pin). The current that flows from the CSx- pin is then given by the following equa-

tion (See Figure 7 - right):

where

50

µA offset allows negative current reading, enabling the device to check for dangerous returning current

between the phases assuring the complete current equalization. From the current information of each

the correction to the PWMx output in order to equalize the current carried by the three phases.

Figure 7. Current reading across LS mosfet: timing (left) and circuit (right) for each phase.

CSx-

CSx+

LGATEx

Rg

Rg

CS_SEL

L

Rg

CSx+

CSx-

PHASEx

OUT

CS_SEL

LS Mosfet Current Sense

Inductor Current Sense

I

CSx-

50

µA

R

ds ON

R

g

------------------ I

PHASEx

⋅

+

50

µAI

INFO x

+

==

I

INFOx

R

dsON

R

g

------------------ I

PHASEx

⋅

=

CSx+

CSx-

LGATEx

50

µA

Rg

Rg