CYUSB2014-BZXI datasheet(28/82 Pages) INFINEON

28 / 82 page

Datasheet

001-52136 Rev. *Y

2022-08-11

EZ-USB FX3

SuperSpeed USB Controller

Pin description

Table 7

CYUSB3012 and CYUSB3014 pin list

BGA

Power domain

I/O

Name

Description

GPIF II interface

Slave FIFO interface [2]

F10

VIO1

I/O

GPIO[0]

DQ[0]

VIO1

I/O

GPIO[1]

DQ[1]

VIO1

I/O

GPIO[2]

DQ[2]

G10

VIO1

I/O

GPIO[3]

DQ[3]

VIO1

I/O

GPIO[4]

DQ[4]

VIO1

I/O

GPIO[5]

DQ[5]

H10

VIO1

I/O

GPIO[6]

DQ[6]

VIO1

I/O

GPIO[7]

DQ[7]

J10

VIO1

I/O

GPIO[8]

DQ[8]/A0 [3]

VIO1

I/O

GPIO[9]

DQ[9]/A1 [3]

K11

VIO1

I/O

GPIO[10]

DQ[10]

L10

VIO1

I/O

GPIO[11]

DQ[11]

K10

VIO1

I/O

GPIO[12]

DQ[12]

VIO1

I/O

GPIO[13]

DQ[13]

VIO1

I/O

GPIO[14]

DQ[14] [4]

VIO1

I/O

GPIO[15]

DQ[15] [4]

VIO1

I/O

GPIO[16]

PCLK

CLK

VIO1

I/O

GPIO[17]

CTL[0]

SLCS#

VIO1

I/O

GPIO[18]

CTL[1]

SLWR#

VIO1

I/O

GPIO[19]

CTL[2]

SLOE#

VIO1

I/O

GPIO[20]

CTL[3]

SLRD#

VIO1

I/O

GPIO[21]

CTL[4]

FLAGA

VIO1

I/O

GPIO[22]

CTL[5]

FLAGB

VIO1

I/O

GPIO[23]

CTL[6]

GPIO

VIO1

I/O

GPIO[24]

CTL[7]

PKTEND#

VIO1

I/O

GPIO[25]

CTL[8]

GPIO

VIO1

I/O

GPIO[26]

CTL[9]

GPIO

VIO1

I/O

GPIO[27]

CTL[10]

GPIO

VIO1

I/O

GPIO[28]

CTL[11]

VIO1

I/O

GPIO[29]

CTL[12]

VIO1

I/O

GPIO[30]

PMODE[0]

VIO1

I/O

GPIO[31]

PMODE[1]

VIO1

I/O

GPIO[32]

PMODE[2]

VIO1

I/O

INT#

INT#/CTL[15]

CTL[15]

Notes

2. Slave FIFO is an example configuration of GPIF II Interface. The Slave FIFO control signal assignments can be

modified using GPIF-II designer tool.

3. For 8-bit data bus configuration, GPIO[8] and GPIO[9] act as address lines.

4. GPIF II can also be configured as a serial interface. The DQ[15] pin becomes a serial output and DQ[14]

becomes a serial input in this mode.

CYUSB2014-BZXI Datasheet(PDF) 28 Page - Infineon Technologies AG

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