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STM32F103XC Datasheet(PDF) 93 Page - STMicroelectronics

Part # STM32F103XC
Description  High-density performance line Arm®-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
PDF  143 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F103XC Datasheet(HTML) 93 Page - STMicroelectronics

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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
135
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 46 and
Table 48, respectively.
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10.
Table 48. I/O AC characteristics(1)
MODEx[1:0]
bit value(1)
Symbol
Parameter
Conditions
Min
Max
Unit
10
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
-
2
MHz
tf(IO)out
Output high to low level
fall time
CL = 50 pF, VDD = 2 V to 3.6 V
-125(3)
ns
tr(IO)out
Output low to high level
rise time
-125(3)
01
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
-
10
MHz
tf(IO)out
Output high to low level
fall time
CL = 50 pF, VDD = 2 V to 3.6 V
-25(3)
ns
tr(IO)out
Output low to high level
rise time
-25(3)
11
Fmax(IO)out Maximum frequency(2)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
-
20
MHz
tf(IO)out
Output high to low level
fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
ns
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
tr(IO)out
Output low to high level
rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
-tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-10
-
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 46.
3. Guaranteed by design.



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