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LEO3910 Datasheet(PDF) 8 Page - STMicroelectronics |
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LEO3910 Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 21 page ![]() 7 Application information To adjust the output voltage, the R2 resistor must be connected between the VO and ADJ pins. The R1 resistor must be connected between ADJ and ground. Resistor values can be derived from the following formula: VO = VADJ (R1+ R2) / R1 The VADJ is typically 1.23 V, controlled by the internal temperature-compensated band gap block. The minimum input voltage is 3 V. The LEO3910 is designed to operate for VI - VO > of the minimum specified dropout. The value of R1, the resistance between ADJ pin and GND, must not be greater than 10 kΩ, in order to keep the output feedback error below 0.2%. A minimum of 0.5 mA IO must be set to ensure perfect no-load regulation. It is advisable to dissipate this current into the divider bridge resistor. The inhibit function switches off the output current very quickly. According to Lenz’s law, the external circuitry reacts with LdI/dt terms which can be of high amplitude in case somewhere a serial coil inductance exists. Large transient voltage would develop on both device terminals. It is advisable to protect the device with Schottky diodes to prevent negative voltage excursions. In the worst case, a 14 V Zener diode could protect the device input. All available VO pins should always be externally interconnected, otherwise the stability and reliability of the device cannot be guaranteed. To ensure regulator stability, input and output capacitors with a minimum 10 μF are mandatory. These capacitors must be connected as close as possible to the device terminals. In the case of high-current operation, an important factor to look at for the reliability target of the space application is the sustainable surge current of the capacitors used. The surge current is known to be one of the major failure mechanisms for these parts, especially when the equipment is turned ON. Tantalum capacitors manufactured per military specifications (MIL-PRF-55365) are established reliability parts targeted for less than 0.001% of failures per 1000 hours (failure rate< 10 FIT). Derating is a means for application engineers of space systems to further reduce the probability of failures by limiting the level of stresses to capacitors during application. Typical derating requirements for solid tantalum capacitors limit the maximum applied voltage to 50% of the rated voltage (VR) and the inrush currents are bounded by additional resistors used in series with the capacitors. In addition, a ceramic capacitor of at least 100nF in parallel to the input and output bulk capacitors must be used for decoupling purposes. A 470 nF polyester capacitors, put close to the regulator between input and ground, helps further improving the LEO3910 reliability by filtering potentially dangerous over voltages spikes coming out during particular conditions. A separate kelvin voltage sensing line provides the ADJ pin with exact load "high potential" information (see Figure 4. Application diagram for remote sensing operation). But variable remote load current consumption induces variable Iq current (Iq is roughly the IO current divided by the hFE of the internal PNP series power element) routed through the parasitic series line resistor RW2. To compensate for this parasitic voltage, resistor RW1 can be introduced to provide the necessary compensating voltage signal to the ADJ pin. A ceramic or polyester 47nF CBYP capacitor between ADJ and VO pins is recommended when the remote sensing technique is implemented. Since the LEO3910 adjustable voltage regulator is manufactured with very high speed bipolar technology (6 GHz fT transistors), the PCB layout must be designed with exceptional care, with very low inductance and low mutually coupling lines. Otherwise, high frequency parasitic signals may be picked up by the device resulting in system self-oscillation. The benefit is an SVR performance extended to far higher frequencies. LEO3910 Application information DS13691 - Rev 2 page 8/21 |
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