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SH79F084BL/016LU Datasheet(PDF) 65 Page - SINOWEALTH Electronic Ltd |
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SH79F084BL/016LU Datasheet(HTML) 65 Page - SINOWEALTH Electronic Ltd |
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65 / 86 page  SH79F084B 65 Table 9.11 PWM Duty Control Register D3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMD PWMD.7 PWMD.6 PWMD.5 PWMD.4 PWMD.3 PWMD.2 PWMD.1 PWMD.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 PWMD[7:0] PWM Duty cycle control, which the controls the first half time of PWM waveform 1. If PWMP ≤ PWMD, PWM pin outputs high level when the PWMS = 0 If PWMP ≤ PWMD, PWM pin outputs low level when the PWMS = 1 2. When PWMD = 00H, PWM pin outputs GND if the PWMS = 0 When PWMD = 00H, PWM pin outputs HIGH if the PWMS = 1 Notes: (1) PWMEN bit can enable the PWM module. (2) PWMSS bit is used to select the P3.7 used as I/O port or PWM output. (3) EPWM in IEN1 register can enable the PWM Timer interrupt. (4) The PWM timer is control by PWMEN bit. If this bit is set to 1, but the PWMSS bit is cleared to ‘0’, the PWM module used as an 8-bit Timer, if the EPWM bit in IEN1 register is set to ‘1’, the interrupt also can be generated. PWM clock t PWM 01 02 03 04 7D 7E 7F 05 80 EF F0 01 02 03 04 PWM output (PWMS=0) PWM output duty cycle = 7FH x t PWM PWM output (PWMS=1) PWM output period cycle = F0H x t PWM PWMP = F0H PWMD = 7FH PWM Output Example PWM clock t PWM 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 01 02 03 04 05 06 07 08 Write PWMP = 0DH Write PWMD = 07H PWM output (PWMS = 0) Period cycle = 0FH x t PWM Duty cycle = 06H x t PWM Period cycle = 0DH x t PWM Duty cycle = 06H x t PWM Duty cycle = 07H x t PWM PWM Output Period or Duty Cycle Changing Example |
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