MEC1632 datasheet(7/636 Pages) MICROCHIP

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DS00001592B-page 7

MEC1632

2.0

GENERAL DESCRIPTION

The MEC1632 is the mixed signal base component of a multi-device advanced I/O controller architecture. The

MEC1632 incorporates a high-performance 32-bit ARC 625D embedded microcontroller with a 192 Kilobyte Embedded

Flash Subsystem, 16 Kilobytes of SRAM, 1 Kilobyte EEPROM emulation, and a 2 Kilobyte EEPROM. The MEC1632

communicates with the system host using the Intel® Low Pin Count bus.

The MEC1632 is the EC Base Component of a split-architecture Advanced I/O Controller system which uses BC-Link

communication protocol to access up to three companion components. The BC-Link protocol is peer-to-peer providing

communication between the MEC1632 embedded controller and registers located in a companion.

The MEC1632 is directly powered by two separate suspend supply planes (VBAT and VTR) and senses a third runtime

power plane (VCC) to provide “instant on” and system power management functions. The MEC1632 also contains an

integrated VTR Reset Interface and a system Power Management Interface that supports low-power states and can

drive state changes as a result of hardware wake events as defined by the MEC1632 Wake Interface.

The MEC1632 defines a software development system interface that includes an MCU Serial Debug Port, a two pin

serial debug port with a 16C550A register interface that is accessible to the EC or to the LPC host and can operate up

to 2 MB/s, a flexible Flash programming interface, a Port 80 BIOS Debug Port, Gang Programmer Interface, and a JTAG

interface. The EC can also drive the JTAG interface as a master.

A top-level block diagram of the MEC1632 is shown below in Figure 2-1. An example of system level connection is

shown in Figure 2-2. A detailed description of the Bus Hierarchy can be found in Section 4.0, "Bus Hierarchy," on

page 55.

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