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MEC1632 Datasheet(PDF) 8 Page - Microchip Technology |
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MEC1632 Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 636 page  MEC1632 DS00001592B-page 8 2012-2018 Microchip Technology Inc. FIGURE 2-1: MEC1632 TOP-LEVEL BLOCK DIAGRAM CPU Voltage VBAT LAD[3:0] LFRAME#, LRESET#, PCI_CLK nSMI SER_IRQ, nCLKRUN nRESET_OUT VCC_PWRGD VR_CAP JTAG_RST# JTAG_TDI JTAG_TMS JTAG_CLK UART_RX UART_TX 16550 (UART) debug port LPC Interface & Host Interrupt Interface JTAG Master and Slave Clock Generation & PM I/F 32 KHz Oscillator VBAT Legacy (Fast_KB) Port 92, CPU_Reset, GateA20 KBRST* A20M* JTAG_TDO vcc Host Configuration Space Access Port Configuration Registers LPC ACCESS EC ACCESS ARC 625D Embedded Controller (EC) Subsystem JTAG ACCESS System Reset Power control Voltage Regulator Reset Interface & Power Mux PS2_CLK[2:0]* ECGP_SIN GPIO* General Purpose I/O Interface General Purpose SPI Interface Notes 1) All blocks powered by VTR except where noted. 2) Signals with unique electrical requirements are highlighted. 3) Asterisks (*) denote multiplexed signal functions. 64 byte memory VBAT VBAT Alarm Wake Hibernation Timer x2 WDT Power Fail Reg VBAT ECGP_SCLK ECGP_SOUT Embedded Flash Flash Program- ming & Securitty GPTP-IN[7:0], GPTP-OUT[7:0] VTR VSS 16-Bit Counter/ Timers ACPI PM MSG I/F ACPI EC MSG I/F (x4) Interrupt Accelerator 16 K Byte SRAM SMBus Interface PWM & Fan Tachometer Interface Input Capture Compare Timer vcc 8042 Host MSG I/F SMB[11:00]_DATA*, SMB0[11:00]_CLK* PS2_DAT[2:0]* PS/2 Interface BCM_DAT[A,B,D] BCM_CLK[A,B,D], BCM_INT#[A,B,D] BC-Link Interface 1 LS-Master 2 HS-Masters KSO[17:0] KSI[7:0] Keyboard Scan 10 Channel DMA Analog Data Acquisition CPU Voltage PECI SB-TSI_CLK SB-TSI_DAT RC_ID Analog RC_ID FLSCLK, FLSOUT, FLSIN,FLSCS# Flash SPI EM I/F RESETO# RESETI# BIOS Debug Port (x2) Mail- box Reg- isters I/F CEC_IN, CEC_OUT HDMI-CEC MSDATA, MSCLK LED[2:0] Blink/Breath LED VCI GANG_DATA[7:0] Gang Programmer GANG_ERR,BUSY,FULL GANG_STROBE,START, MODE UART_CLK XTAL2 XTAL1 VBAT RTC VCI_OUT, BGPO[5:0] VCI_IN[5:0]#, VCI_OVRD_IN Trace FIFO Debug Port |
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