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MEC1632 Datasheet(PDF) 1 Page - Microchip Technology

Part # MEC1632
Description  Low Power 32-Bit Mobile Embedded Controller
PDF  636 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MEC1632 Datasheet(HTML) 1 Page - Microchip Technology

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 2012-2018 Microchip Technology Inc.
DS00001592B-page 1
Highlights
• 3.3V Operation
• ACPI Compliant
• LPC Interface
• VTR (standby) and VBAT Power Planes
- Low Standby Current in Sleep Mode
• Configuration Register Set
- Compatible with ISA Plug-and-Play Standard
- EC-Programmable Base Address
• ARC-625D Embedded Controller (EC)
- 16 KB Single Cycle 32-bit Wide Dual-ported
SRAM, Accessible as Closely Coupled Data
Memory and Instruction Memory
- 4KB Boot ROM
- 32 x 32
 64 Fast Multiply
- Divide Assist and Saturation Arithmetic
- Maskable Interrupt Aggregator/Accelerator
Interface
- Maskable Hardware Wake-Up Events
- Sleep mode
- JTAG Debug Port, Includes JTAG Master
- MCU Serial Debug Port
-1
S Delay Register
- 10-Channel DMA Interface Supports SMBus
Controllers and EC/Host GP-SPI Controllers
• Embedded Flash
- 192 KB user space, 32-bit Access, 10 K
Cycles Endurance
- Flash Security Enhancements
–4K Boot Block Protection
–Direct JTAG and Direct LPC-protected (2) Pages at
or Near Top of Memory for Password Protection
- Multiple Flash Programming Options
–JTAG programmable
–BIOS programmable
–Programmable by EC at Power-on Using UART
–Programmable on a Gang Programmer via Gang-
programmer Interface
• Embedded Non-volatile Read/Write Memory
- 2 KB of EEPROM, Single Byte Access, 250K
Cycles Endurance
- 8-byte Block Erasable, 128 Blocks
- Independent of main Flash memory
• Legacy Support
- Fast GATEA20 & Fast CPU_RESET
• System to EC Message Interface
- 8042 Style Host Interface
- Embedded Memory Interface
- Host Serial or Parallel IRQ Source
- Provides Two Windows to On-Chip SRAM for Host
Access
- Two Register Mailbox Command Interface
- Host Access of Virtual Registers Without EC
Intervention
- Mailbox Registers Interface
- Thirty-two 8-Bit Scratch Registers
- Two Register Mailbox Command Interface
- Two Register SMI Source Interface
- ACPI Embedded Controller Interface
- Four Instances
- 1 or 4 Byte Data transfer capable
- Full-duplex Register Access
- ACPI Power Management Interface
- SCI Event-Generating Functions
• Battery Backed Resources
- Power-Fail Status Register
- 32 KHz Clock Generator
- Week Alarm Timer Interface with Program-
mable Wake-up from 1ms to 45 Days
- VBAT-Powered Control Interface
- Six Wake-up Input Signals
- Optional Latching of Wake-up Inputs
- VBAT-Backed 64 Byte Memory
• Four EC-based SMBus 2.0 Host Controllers
- Allows Master or Dual Slave Operation
- Controllers are Fully Operational on Standby
Power
- DMA-driven I2C Network Layer Hardware
-I2C Datalink Compatibility Mode
- Multi-Master Capable
- Supports Clock Stretching
- Programmable Bus Speed up to 400KHz
- Hardware Bus Access “Fairness” Interface
- SMBus Time-outs Interface
- AMD-TSI Port
- 12 Ports Assignable to Any Controller
- 3 SMBus Isolation Switches
- Three Pairs of Ports Can Be Joined
• PECI Interface 3.0
MEC1632
Low Power 32-Bit Mobile Embedded Controller


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