STM32H753II datasheet(358/361 Pages) STMICROELECTRONICS

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DS12117 Rev 8

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STM32H753xI

Revision history

359

4-Mar-2022

Added reference to errata sheet ES0392 in Section 1: Introduction.

Section 2: Description

Table 2: STM32H753xI features and peripheral counts: removed note indicating that

packages are under development, split number of ADC channels into Direct, Fast

and Slow channels; and added number of wakeup and tamper pins.

Changed APB1 and APB2 maximum frequency to 120 MHZ in Figure 1:

STM32H753xI block diagram.

Section 3: Functional overview

Added connection between SDMMC2 and D2-to-D3 AHB bus in Figure 3:

STM32H753xI bus matrix.

Updated Section 3.27: True random number generator (RNG).

Added Full-duplex mode in Section 3.34: Serial peripheral interfaces

(SPI)/integrated interchip sound interfaces (I2S).

Updated number of microphones that can be supported by the SAI in Section 3.35:

Serial audio interfaces (SAI).

Section 5: Pin descriptions

Updated J1, F1, F2 and G2 signals and added notes 2, 3 and 4 in Figure 11:

TFBGA240+25 ballout.

Removed FDCAN1_RXFD_MODE, FDCAN1_TXFD_MODE,

FDCAN2_RXFD_MODE and FDCAN2_TXFD_MODE functions from Table 8:

Pin/ball definition and all alternate function tables.

Additional modifications made on Table 8: Pin/ball definition: added note to

VDD50USB, change PB1 I/O structure to TT_a, replaced PI8 WKUP3 additional

function by WKUP2, replaced PC13 WKUP2 additional function by WKUP3,

changed F1 and G2 to VSS.

Section 6: Electrical characteristics (rev Y):

– Updated Section 6.2: Absolute maximum ratings introduction to add device

mission profile.

– Updated Figure 14: Power supply scheme.

– Power dissipation (PD) removed from Table 23: General operating conditions

since this parameter is redundant with

ΘJA thermal resistance.

– Updated Table 41: High-speed external user clock characteristics.

– Table 52: Flash memory programming: removed reference to single bank

configuration in title and updated tERASE128KB typical and maximum values.

– Added reference to AN4899 in Section 6.3.15: I/O port characteristics. Updated

Fmax for speed 10 and 11 in Table 62: Output timing characteristics (HSLV OFF).

Updated notes in Table 63: Output timing characteristics (HSLV ON).

– Updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH) in Table 73:

Synchronous multiplexed NOR/PSRAM read timings. Changed t(NWAIT-CLKH) to

tsu(NWAIT-CLKH) and updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-

CLKH) in Table 75: Synchronous non-multiplexed NOR/PSRAM read timings.

– Replaced FMC_CLK by FMC_SDCLK in Section : SDRAM waveforms and timings

– Updated tsu(SDCLKH _Data) and th(SDCLKH _Data) in Table 79: SDRAM read timings

and Table 80: LPSDR SDRAM read timings.

Table 230. Document revision history

Date

Revision

Changes

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