STM32H753II datasheet(359/361 Pages) STMICROELECTRONICS

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Revision history

STM32H753xI

358/360

DS12117 Rev 8

4-Mar-2022

(continued)

Section 6: Electrical characteristics (rev Y) (continued)

– Updated ts(IN) and th(IN) in Table 83: QUADSPI characteristics in SDR mode

tsr(IN)/tsf(IN) and thr(IN)/thf(IN) in Table 84: QUADSPI characteristics in DDR mode.

Updated Figure 38: Quad-SPI timing diagram - DDR mode.

– Updated maximum sampling time (tS) value in Table 86: ADC characteristics.

Updated Figure 39: ADC accuracy characteristics, Figure 40: Typical connection

diagram when using the ADC with FT/TT pins featuring analog switch function and

Figure 41: Power supply and reference decoupling (VREF+ not connected to

VDDA).

– Updated TL maximum value in Table 91: Temperature sensor characteristics.

– Updated fDFSDMCLK and DuCyCKOUT in Table 99: DFSDM measured timing - 1.62-

3.6 V.

– Updated fTIMxCLK to match an APB1/2 maximum frequency of 120 MHZ in

Table 102: TIMx characteristics.

– Updated tsu(MI) and th(MI) minimum values in Table 105: SPI dynamic

characteristics.

– Updated tISU, tIH, tISUD and tIHD in Table 109: Dynamic characteristics: SD / MMC

characteristics, VDD = 2.7 to 3.6 V, and tISU, tIH in Table 110: Dynamic

characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V. Updated Figure 58:

DDR mode.

Section 7: Electrical characteristics (rev V):

– Updated Figure 67: Power supply scheme.

– Updated Section 7.2: Absolute maximum ratings introduction to device mission

profile.

– Power dissipation (PD) removed from Table 121: General operating conditions

since this parameter is redundant with

ΘJA thermal resistance.

– Replaced Min VDD by Min VDDLDO in Table 122: Supply voltage and maximum

frequency configuration.

– Updated Table 138: High-speed external user clock characteristics.

– Table 149: Flash memory programming: removed reference to single bank

configuration in title, and updated tERASE128KB.

– Updated condition related to

frcc_c_ck in Section : On-chip peripheral current

consumption.

– Added reference to AN4899 in Section 7.3.15: I/O port characteristics. Updated

Fmax for speed 10 and 11 in Table 159: Output timing characteristics (HSLV OFF).

Changed capacitance value for speed 10 and tr/tf, and speed for 11 and tr/tf/Fmax

Table 160: Output timing characteristics (HSLV ON).

– Updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH) in Table 170:

Synchronous multiplexed NOR/PSRAM read timings. Changed t(NWAIT-CLKH) to

tsu(NWAIT-CLKH) and updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-

CLKH) in Table 172: Synchronous non-multiplexed NOR/PSRAM read timings.

Updated tsu(SDCLKH _Data) and th(SDCLKH _Data) in Table 176: SDRAM read timings

and Table 177: LPSDR SDRAM read timings. Replaced FMC_CLK by

FMC_SDCLK in Section : SDRAM waveforms and timings.

– Updated ts(IN) and th(IN) in Table 180: QUADSPI characteristics in SDR mode and

tsr(IN)/tsf(IN) and thr(IN)/thf(IN) in Table 181: QUADSPI characteristics in DDR mode.

Updated Figure 90: Quad-SPI timing diagram - DDR mode.

Table 230. Document revision history

Date

Revision

Changes

STM32H753II Datasheet(PDF) 359 Page - STMicroelectronics

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