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STM32L010R8 Datasheet(PDF) 66 Page - STMicroelectronics

Part # STM32L010R8
Description  Value line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0,64-Kbyte Flash memory, 8-Kbyte SRAM, 256-byte EEPROM, ADC
PDF  92 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L010R8 Datasheet(HTML) 66 Page - STMicroelectronics

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Electrical characteristics
STM32L010K8 STM32L010R8
66/92
DS12325 Rev 3
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin.
•
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 47.
Table 45. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
value(1)
1. Guaranteed by characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming
to ANSI/JEDEC JS-001
2
2000
V
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = +25 °C, conforming
to ANSI/ESD STM5.3.1
C4
500
Table 46. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +85 °C conforming to JESD78A
II level A



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