STM32W108HB datasheet(113/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Serial interfaces

Doc ID 16252 Rev 14

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Characters received are stored in the receive FIFO. Receiving characters sets the RXNE bit

in the SCx_SPISR register, to indicate that characters can be read from the receive FIFO.

Characters received while the receive FIFO is full are dropped, and the OVF bit in the

SCx_SPISR register is set. The receive FIFO hardware generates the OVR interrupt, but the

DMA register will not indicate the error condition until the receive FIFO is drained. Once the

DMA marks a receive error, two conditions will clear the error indication: setting the

appropriate TXRST/RXRST bit in the SCx_DMACR register, or loading the appropriate

DMA buffer after it has unloaded.

Receiving a character causes the serial transmission of a character pulled from the transmit

FIFO. When the transmit FIFO is empty, a transmit underrun is detected (no data in transmit

FIFO) and the UDR bit in the SCx_ISR register is set. Because no character is available for

serialization, the SPI serializer retransmits the last transmitted character or a busy token

(0xFF), determined by the RPTEN bit in the SCx_SPICR register.

When the transmit FIFO and the serializer are both empty, writing a character to the transmit

FIFO clears the IDLE bit in the SCx_SPISR register. This indicates that not all characters

have been transmitted. If characters are written to the transmit FIFO until it is full, the TXE

bit in the SCx_SPISR register is cleared. Shifting out a transmit character to the MISO pin

causes the TXE bit in the SCx_SPISR register to get set. When the transmit FIFO empties

and the last character has been shifted out, the IDLE bit in the SCx_SPISR register is set.

The SPI slave controller must guarantee that there is time to move new transmit data from

the transmit FIFO into the hardware serializer. To provide sufficient time, the SPI slave

controller inserts a byte of padding at the start of every new string of transmit data. After

slave select asserts and the RXNE bit in the SCx_SPISR register gets set at least once, the

following operation holds true until slave select deasserts. Whenever the transmit FIFO is

empty and data is placed into the transmit FIFO, either manually or through DMA, the SPI

hardware inserts a byte of padding onto the front of the transmission as if this byte was

placed there by software. The value of the byte of padding that is inserted is selected by the

RPTEN bit in the SCx_SPICR register.

9.4.3

DMA

The DMA Channels section describes how to configure and use the serial receive and

transmit DMA channels.

When using the receive DMA channel and nSSEL transitions to the high (deasserted) state,

the active buffer's receive DMA count register (SCx_DMARXCNTAR/SCx_DMARXCNTBR)

is saved in the SCx_DMARXCNTSAVEDR register. SCx_DMARXCNTSAVEDR is only

written the first time nSSEL goes high after a buffer has been loaded. Subsequent rising

edges set a status bit but are otherwise ignored. The 3-bit field NSSS in the SCx_DMASR

whether or not another rising edge occurred on nSSEL.

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