STM32W108HB datasheet(114/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

9.4.4

Interrupts

SPI slave controller second level interrupts are generated on the following events:

●

Transmit FIFO empty and last character shifted out (depending on SCx_ICR, either the

0 to 1 transition or the high level of IDLE)

●

Transmit FIFO changed from full to not full (depending on SCx_ICR, either the 0 to 1

transition or the high level of TXE)

●

Receive FIFO changed from empty to not empty (depending on SCx_ICR, either the 0

to 1 transition or the high level of RXNE)

●

Transmit DMA buffer A/B complete (1 to 0 transition of TXAACK/TXBACK)

●

Receive DMA buffer A/B complete (1 to 0 transition of RXAACK/RXBACK)

●

Received and lost character while receive FIFO was full (receive overrun error)

●

Transmitted character while transmit FIFO was empty (transmit underrun error)

To enable CPU interrupts, set desired interrupt bits in the second level SCx_IER register.

9.5

Inter-integrated circuit interfaces (I2C)

Both STM32W108 serial controllers SC1 and SC2 include an Inter-integrated circuit

interface (I2C) master controller with the following features:

●

Uses only two bidirectional GPIO pins

●

Programmable clock frequency (up to 400 kHz)

●

Supports both 7-bit and 10-bit addressing

●

Compatible with Philips' I2C-bus slave devices

The I2C master controller uses just two signals:

●

SDA (Serial Data) - bidirectional serial data

●

SCL (Serial Clock) - bidirectional serial clock

Table 25 lists the GPIO pins used by the SC1 and SC2 I2C master controllers. Because the

pins are configured as open-drain outputs, they require external pull-up resistors.

Direction

GPIO configuration

SC1 pin

SC2 pin

Table 25.

I2C Master GPIO Usage

Parameter

SDA

SCL

Input / Output

Alternate Output

(open drain)

Alternate Output

(open drain)

PB1

PB2

PA1

PA2

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