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STM32W108CB Datasheet(PDF) 146 Page - STMicroelectronics |
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STM32W108CB Datasheet(HTML) 146 Page - STMicroelectronics |
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146 / 278 page ![]() Serial interfaces STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 146/278 Doc ID 16252 Rev 14 9.12.12 Serial controller DMA status register (SCx_DMASR) Address offset: 0xC82C (SC1_DMASR) and 0xC02C (SC2_DMASR) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NSSS FEB FEA PEB PEA OVRB OVRA TX BACK TX AACK RX BACK RX AACK r r r r r rr rr rr r r Bits [31:13] Reserved, must be kept at reset value Bits [12:10] NSSS: Status of the receive count saved in SCx_DMARXCNTSAVEDR (SPI slave mode) when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is reset. 0: No count was saved because nSSEL did not deassert 2: Buffer A's count was saved, nSSEL deasserted once 3: Buffer B's count was saved, nSSEL deasserted once 6: Buffer A's count was saved, nSSEL deasserted more than once 7: Buffer B's count was saved, nSSEL deasserted more than once 1, 4, 5: Reserved, must be kept at reset value Bit 9 FEB: Frame error B flag This bit is set when DMA receive buffer B reads a byte with a frame error from the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. 0: No DMA buffer B frame error 1: DMA buffer B frame error Note: Not used in SC2 Bit 8 FEA: Frame error A flag This bit is set when DMA receive buffer A reads a byte with a frame error from the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. 0: No DMA buffer A frame error 1: DMA buffer A frame error Note: Not used in SC2 Bit 7 PEB: Parity error B flag This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. 0: No DMA buffer B parity error 1: DMA buffer B parity error Note: Not used in SC2 Bit 6 PEA: Parity error A flag This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. 0: No DMA buffer A parity error 1: DMA buffer A parity error Note: Not used in SC2 |
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