STM32W108CB datasheet(158/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

The auto-reload register is buffered. Writing to or reading from the auto-reload register

accesses the buffer register. The contents of the buffer register are transferred into the

shadow register permanently or at each update event (UEV), depending on the auto-reload

buffer enable bit (ARPE) in the TIMx_CR1 register. The update event is generated when

both the counter reaches the overflow (or underflow when down-counting) and when the

UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. Update

event generation is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the

counter enable bit (CEN) in the TIMx_CR1 register is set. Refer also to the slave mode

controller description in the Timers and External Trigger Synchronization section to get more

details on counter enabling.

Note that the actual counter enable signal CNT_EN is set one clock cycle after CEN.

Note:

When the STM32W108 enters debug mode and the ARM® Cortex-M3 core is halted, the

counters continue to run normally.

Prescaler

The prescaler can divide the counter clock frequency by power of two from 1 through 32768.

It is based on a 16-bit counter controlled through the 4-bit PSC[3:0] in the TIMx_PSC

raised to the power PSC[3:0]:

CK_CNT

CK_PSC

2 ^ PSC[3:0]

()

⁄

It can be changed on the fly as this control register is buffered. The new prescaler ratio is

used starting at the next update event.

Figure 16 gives an example of the counter behavior when the prescaler ratio is changed on

the fly.

Figure 16.

Counter timing diagram with prescaler division change from 1 to 4

STM32W108CB Datasheet(PDF) 158 Page - STMicroelectronics