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STM32W108CB Datasheet(PDF) 181 Page - STMicroelectronics |
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STM32W108CB Datasheet(HTML) 181 Page - STMicroelectronics |
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181 / 278 page ![]() STM32W108HB STM32W108CC STM32W108CB STM32W108CZ General-purpose timers Doc ID 16252 Rev 14 181/278 10.1.13 Timers and external trigger synchronization The timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode Reset mode reinitializes the counter and its prescaler in response to an event on a trigger input. Moreover, if the URS bit in the TIMx_CR1 register is low, an update event is generated. Then all the buffered registers (TIMx_ARR, TIMx_CCRy) are updated. In the following example, the up-counter is cleared in response to a rising edge on the TI1 input: ● Configure the channel 1 to detect rising edges on TI1: Configure the input filter duration. In this example, no filter is required so IC1F = 0000. The capture prescaler is not used for triggering, so it is not configured. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P = 0 in the TIMx_CCER register to validate the polarity, and detect rising edges only. ● Configure the timer in Reset mode by writing SMS = 100 in the TIMx_SMCR register. Select TI1 as the input source by writing TS = 101 in the TIMx_SMCR register. ● Start the counter by writing CEN = 1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until the TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (the TIE bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in the TIMx_IER register). Figure 41 shows this behavior when the auto-reload register TIMx_ARR = 0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on the TI1 input. Figure 41. Control circuit in Reset mode 00 Counter clock = CK_CNT = CK_PSC Counter register 01 02 03 00 01 02 03 32 33 34 35 36 UG TI1 31 30 TIE |
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