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STM32W108CB Datasheet(PDF) 195 Page - STMicroelectronics |
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STM32W108CB Datasheet(HTML) 195 Page - STMicroelectronics |
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195 / 278 page  STM32W108HB STM32W108CC STM32W108CB STM32W108CZ General-purpose timers Doc ID 16252 Rev 14 195/278 Bit 1 UDIS: Update Disable 0: An update event is generated as soon as a counter overflow occurs, a software update is generated, or a hardware reset is generated by the slave mode controller. Shadow registers are then loaded with their buffer register values. 1: An update event is not generated and shadow registers keep their value (TIMx_ARR, TIMx_PSC, TIMx_CCRy). The counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter Enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. Trigger mode sets the CEN bit automatically through hardware. |
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