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STM32W108CB Datasheet(PDF) 223 Page - STMicroelectronics

Part # STM32W108CB
Description  High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory
PDF  278 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108CB Datasheet(HTML) 223 Page - STMicroelectronics

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Analog-to-digital converter
Doc ID 16252 Rev 14
223/278
Table 40 shows the options for ADC sample times and the significant bits in the conversion
results.
Note:
ADC sample timing is the same whether the STM32W108 is using the 24 MHz HSE OSC or
the 12 MHz HSI RC oscillator. This facilitates using the ADC soon after the CPU wakes from
deep sleep, before switching to the crystal oscillator.
11.1.7
Operation
Setting the ADC_EN bit in the ADC_CR register enables the ADC; once enabled, it performs
conversions continuously until it is disabled. If the ADC had previously been disabled, a 21
µs analog startup delay is imposed before the ADC starts conversions. The delay timing is
performed in hardware and is simply added to the time until the first conversion result is
output.
When the ADC is first enabled, and or if any change is made to ADC_CR after it is enabled,
the time until a result is output is double the normal sample time. This is because the ADC’s
internal design requires it to discard the first conversion after startup or a configuration
change. This is done automatically and is hidden from software except for the longer timing.
Switching the processor clock between the RC and crystal oscillator also causes the ADC to
go through this startup cycle. If the ADC was newly enabled, the analog delay time is added
to the doubled sample time.
If the DMA is running when ADC_CR is modified, the DMA does not stop, so the DMA buffer
may contain conversion results from both the old and new configurations.
Table 40.
ADC sample times
SMP[2:0]
Sample
clocks
Sample time (µs)
Sample frequency (kHz)
Significant
bits
1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock
032
325.33
31.3
188
5
1
64
64
10.7
15.6
93.8
6
2
128
128
21.3
7.81
46.9
7
3
256
256
42.7
3.91
23.4
8
4
512
512
85.3
1.95
11.7
9
5
1024
1024
170
0.977
5.86
10
6
2048
2048
341
0.488
2.93
11
7
4096
4096
682
0.244
1.47
12



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