STM32W108CB datasheet(274/278 Pages) STMICROELECTRONICS

274 / 278 page

Revision history

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

274/278

Doc ID 16252 Rev 14

03-Sep-2012

(continued)

Section 6.2.4: added Reset (RST) register map.

Section 6.3: Clocks: added note beneath bullets points (before

Figure 7).

Section 6.3.6: added Low-speed internal 10 KHz clock (LSI10K)

control register (CLK_LSI10KCR), Low-speed internal 1 KHz clock

control register (CLK_LSI1KCR), High-speed external clock control

(CLK_HSICR), High-speed external clock comparator register

(CLK_HSECOMPR), Clock period control register

(CLK_PERIODCR), Clock period status register (CLK_PERIODSR),

Clock dither control register (CLK_DITHERCR), High-speed external

clock control register 2 (CLK_HSECR2), CPU clock control register

(CLK_CPUCR), Clock switching (CLK) register map.

Added Section 6.4.5.

Section 6.4.5: Added Sleep timer force interrupt register

(SLPTMR_IFR), MACTimer counter register (MACTMR_CNTR),

MACTimer counter register (MACTMR_CR) and MAC timer

(MACTMR)/Watchdog (WDG)/Sleeptimer(SLPTMR) register map.

Section 6.5.1: updated last bullet point.

Section 6.5.2: updated bullet points.

Added Section 6.5.5: Power management registers.

Section 8.1.1: updated paragraph concerning configuration registers.

Added Table 8.5.10: PC TRACE or debug select register

(GPIO_PCTRACECR).

Added Table 8.5.13: General-purpose input/output (GPIO) register

map.

Section 9.4.1: removed “see table 86).

Table 22: SPI master mode formats, Table 24: SPI slave mode

formats, and Figure 27: I2C master frame segments: updated

heading lines and removed footnote.

Removed Section 9.10: SPI slave mode registers.

Section 9.12.5 to Section 9.12.15: Bit ranges changed to [12:0].

Added Section 9.12.17: Serial interface (SC1/SC2) register map.

Section 10.1.1: updated Prescaler section.

Section 10.3.8 and Section 10.3.9: separated register descriptions

into “output compare mode” and “input capture mode”.

Added Section 10.3.20: General-purpose timers 1 and 2

(TIM1/TIM2) register map.

Section 11.1.8: updated information regarding the VDD_PADSA

regulator

Section 11.3.8: Bit range changed to [12:0].

Section 11.3.10: Bit range changed to [13:1].

Added Section 11.3.12: Analog-to-digital converter (ADC) register

map.

Section 12: Interrupts: updated section and removed register

descriptions.

Added Section 12.2: Management interrupt registers.

Added Section 14.4: SPI interface characteristics.

Table 73.

Document revision history (continued)

Date

Revision

Changes

STM32W108CB Datasheet(PDF) 274 Page - STMicroelectronics

STM32W108CB Datasheet(HTML) 274 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL