If the low-side sinking current limit is exceeded, the low-side MOSFET is turned off. In this scenario, both

MOSFETs are off until the start of the next cycle.

7.3.10 Thermal Shutdown

The device goes into thermal shutdown after the junction temperature exceeds typically 170°C with a 20°C

hysteresis.

7.4 Device Functional Modes

7.4.1 Fixed Frequency Pulse Width Modulation

To minimize output voltage ripple, the device operates in fixed frequency PWM operation down to no load. The

switching frequency of 1 MHz or 2.2 MHz is selected using the S-CONF pin.

7.4.2 Low Duty Cycle Operation

For high input voltages or low output voltages, the 70-ns minimum on-time limits the maximum input to output

voltage difference and the switching frequency selected. When the minimum on-time is reached, the output

voltage rises above the regulation point. Refer to Table 8-2 for detailed design recommendations.

7.4.3 High Duty Cycle Operation (100% Duty Cycle)

The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode,

the high-side MOSFET switch is constantly turned on. The minimum input voltage to maintain output voltage

regulation, depending on the load current and the output voltage level, is calculated as:

(min)

(min)

(

)

(

)

IN

OUT

OUT

DS ON

L

V

V

I

R

R

u

(2)

where

• VOUT(min) is the minimum output voltage the load can accept

• IOUT is the output current

• RDS(ON) is the RDS(ON) of the high-side MOSFET

• RL is the DC resistance of the inductor used,

76 mΩ for the TPSM8291x

To maintain fixed frequency switching, the device requires a minimum off-time of 50 ns (typical), 60 ns

(maximum). If this limit is reached during a switching pulse, the device skips switching pulses to maintain output

voltage regulation. If the input voltage decreases further, the device enters 100% mode.

7.4.4 Second Stage L-C Filter Compensation (Optional)

Most low-noise and low-ripple applications use a ferrite bead and bypass capacitor before the load. Using a

second L-C filter is especially useful for low-noise and low-ripple applications with constant load current such as

ADCs, DACs, and Jitter Cleaner. The second stage L-C filter is optional, and the device can be used without

this filter. Without the filter, the device has a low output voltage noise of typically 16.6 μVRMS shown in Figure

6-29 with an output voltage ripple of 280 μVRMS shown in Figure 6-10. The second stage L-C filter attenuates

the output voltage ripple by another approximately 30 dB shown in Figure 6-12. To improve load regulation, the

device can remote sense the output voltage after the second stage L-C filter and is internally compensated for

the additional double pole generated by the L-C filter.

To keep the second stage L-C filter as small as possible, the internal compensation is optimized for a 10-nH

to 50-nH inductance. A small ferrite bead or even a PCB trace provides sufficient inductance for output voltage

ripple filtering. See Section 8.2.2.2.3 for details.

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TPSM82913

SLVSGJ4A – OCTOBER 2022 – REVISED DECEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

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