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FT900

/1/2/3 Revision C Embedded Microcontroller Datasheet

Version 1.0

Document No. BRT_000172 Clearance No.: BRT#087

4.5

Interrupt

The FT900/1/2/3 interrupt controller handles 32 interrupt inputs. When an interrupt occurred, the

Interrupt Service Route (ISR) will process this event via the CPU. The ISR vector range is from 0 to 31,

which corresponds to interrupt 0 to 31. See Table 4-1 information.

Each interrupt shall be assigned the interrupt vector number and priority before use. By default, the

highest priority interrupt is interrupt 0, and the lowest is interrupt 31. However, the interrupt priority can

be rearranged by register settings and also allows multiple interrupts at the same priority.

To prevent the loss and delay of high priority interrupts, the FT900/1/2/3 series uses nested interrupts if

enabled. Nested interrupts allow interrupt requests of a high priority to pre-empt interrupt requests of a

lower priority. FT900/1/2/3 series supports up to 16-levels deep of nested interrupts.

The interrupt controller has a global interrupt mask bit to temporarily block all interrupts. If this bit is set

to “1”, then with the exception of an interrupt assigned priority as “0”, which is a non-maskable interrupt

(NMI) input, all interrupts are masked.

See Table 4-1 for FT900/1/2/3 series default interrupt priority.

Peripherals of Interrupt

Interrupt Vector Index

Default Priority

Power Management

0 (NMI)

USB2.0 Host Controller

USB2.0 Peripheral Controller

Ethernet Controller

SD Host Controller

CAN Bus 0

CAN Bus 1

Camera

SPI Master

SPI Slave 0

SPI Slave 1

I2C 0

I2C 1

UART 0

UART 1

I2S Bus

PWM

Timers

GPIO

RTC

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