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MIC33M650YMP Datasheet(PDF) 13 Page - Microchip Technology |
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MIC33M650YMP Datasheet(HTML) 13 Page - Microchip Technology |
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13 / 32 page ![]() 2019 Microchip Technology Inc. DS20006253A-page 13 MIC33M650 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Number Symbol Description 2, 3, 4, 5, 23, 24, 39, 40 PGND Power Ground. PGND is the ground path for the MIC33M650 power module. 1, 53 AUX_PVIN Auxiliary Power Input Voltage Pin. Connect externally to PVIN. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 SW Switch Node Pin. SW connects to the internal MOSFETs and inductor. Do not connect any external load to this point. 41, 42 PVIN Power Supply Voltage Pin. 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38 OUT Output Side Connection Pin. 43, 44 SVIN Analog Voltage Input Pin. SVIN is the power to the internal reference and control sections of the MIC33M650. Internally connected to PVIN through a 10W resistor. 46, 47 AUX_AGND Auxiliary Analog Ground Pin. Connect externally to AGND. 45 VSEL2 Output Voltage Selection Control 2 (Input) Pin. The logic state of VSEL1 and VSEL2 selects the output voltage. This input has three digital states: High, Low and Floating. 48 VSEL1 Output Voltage Selection Control 1 (Input) Pin. The logic state of VSEL1 and VSEL2 selects the output voltage. This input has three digital states: High, Low and Floating. 49 EN Enable (Input) Pin. Logic high enables the operation of the regulator. The EN pin should not be left floating. 50 PG Power Good (Output) Pin. This is an open-drain output that indicates when the output voltage is higher than the 91% limit. 51 VOUT Output Voltage Sense (Input) Pin. This pin is used to remote sense the output voltage. Connect VOUT as close to the output capacitor as possible to sense the output voltage. 52 AGND Analog Ground Pin. AGND is the internal signal ground for all low-power circuits. 54 EP_OUT Exposed Thermal Pad. Internally connected to OUT. 55 EP_SW Exposed Thermal Pad. Internally connected to SW. 56 EP_PGND Exposed Thermal Pad. Internally connected to PGND. 57 EP_PVIN Exposed Thermal Pad. Internally connected to PVIN. |
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