MIC33M650YMP datasheet(14/32 Pages) MICROCHIP

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MIC33M650

DS20006253A-page 14

 2019 Microchip Technology Inc.

3.1

Power Ground Pin (PGND)

PGND is the ground path for the MIC33M650 buck

converter power stage. The PGND pin connects to the

sources of the low-side N-Channel MOSFETs, the neg-

ative terminals of input capacitors and the negative

terminals of output capacitors. The loop for the Power

Ground must be as small as possible and separate

from the Analog Ground (AGND) loop.

3.2

Switch Node Pin (SW)

Switching node output pin which connects to the

internal MOSFETs and inductor. This is a high-

frequency connection; therefore, traces should be kept

as short and as wide as practical.

3.3

Power Supply Voltage Pin (PVIN)

Input supply to the source of the internal high-side

P-channel MOSFET. The PVIN operating voltage range

is from 2.4V to 5.5V. An input capacitor between PVIN

and the PGND pin is required and placed as close to the

IC as possible.

3.4

Output Side Connection Pins

(OUT)

Output side connection of the internal inductor. The

output capacitors must be connected from this pin

group to GND, as close to the module as possible.

3.5

Analog Voltage Input Pin (SVIN)

This pin is the power to the internal reference and

control sections of the MIC33M650. It is internally

connected to PVIN through a 10 resistor.

3.6

Output Voltage Selection Control

Pins (VSEL1, VSEL2)

Output Voltage Selection Control (Input). The logic

state of VSEL1 and VSEL2 selects the output voltage.

This input has three digital states: High, Low and

Floating. See Table 4-1.

3.7

Enable Pin (EN)

Logic high enables the regulator’s operation. Logic low

shuts down the device. In the OFF state, the supply

current of the device is greatly reduced (typically,

1.5 µA). The EN pin should not be left open.

3.8

Power Good Pin (PG)

This is an open-drain output that indicates when the

output voltage is higher than the 91% limit. There is a

4% hysteresis; therefore, PG will return low when the

output voltage falls below 87% of the target regulation

voltage.

3.9

Output Voltage Sense Pin (VOUT)

This pin is used to remote sense the output voltage.

Connect to VOUT as close to the output capacitor as

possible to sense the output voltage. It also provides

the path to discharge the output through an internal

 resistor when the device is disabled.

3.10

Analog Ground Pin (AGND)

Internal signal ground for all low-power circuits.

Connect to ground plane. For best load regulation, the

connection path from AGND to the output capacitor

ground terminal must be free from parasitic voltage

drops.

3.11

Auxiliary Analog Ground Pins

(AUX_AGND)

Connect these pins to AGND to make use of the internal

decoupling capacitor for SVIN pin filtering.

3.12

Auxiliary Input Voltage Pins

(AUX_PVIN)

Connect these pins to PVIN to make use of the internal

10 µF capacitor for PVIN filtering/decoupling.

3.13

OUT Exposed Pad (EP_OUT)

It is electrically connected to the OUT pins. It must be

externally connected to the output power connection.

3.14

SW Exposed Pad (EP_SW)

It is electrically connected to the SW node.

3.15

PGND Exposed Pad (EP_PGND)

It is electrically connected to the PGND pins. It must be

connected with thermal vias to the ground plane to

ensure adequate heat sinking.

3.16

PVIN Exposed Pad (EP_PVIN)

It is electrically connected to the PVIN pins. It must be

connected to the input power connection.

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