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UPSD3422 Datasheet(PDF) 56 Page - STMicroelectronics

Part # UPSD3422
Description  Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic
PDF  300 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3422 Datasheet(HTML) 56 Page - STMicroelectronics

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UPSD34xx instruction set summary
UPSD3422, UPSD3433, UPSD3434, UPSD3454
56/300
CJNE
@Ri, #data,
rel
Compare immediate to indirect, jump if not equal
3 byte/2 cycle
DJNZ
Rn, rel
Decrement register and jump if not zero
2 byte/2 cycle
DJNZ
direct, rel
Decrement direct byte and jump if not zero
3 byte/2 cycle
1.
All mnemonics copyrighted ©Intel Corporation 1980.
Table 11.
Miscellaneous instruction set
Mnemonic(1) and Use
1.
All mnemonics copyrighted ©Intel Corporation 1980.
Description
Length/Cycles
Miscellaneous
NOP
No operation
1 byte/1 cycle
Table 12.
Notes on instruction set and addressing modes
Rn
Register R0 - R7 of the currently selected register bank.
direct
8-bit address for internal 8032 DATA SRAM (locations 00h - 7Fh) or SFR registers
(locations 80h - FFh).
@Ri
8-bit internal 8032 SRAM (locations 00h - FFh) addressed indirectly through contents of
R0 or R1.
#data
8-bit constant included within the instruction.
#data16 16-bit constant included within the instruction.
addr16
16-bit destination address used by LCALL and LJMP.
addr11
11-bit destination address used by ACALL and AJMP.
rel
Signed (two-s compliment) 8-bit offset byte.
bit
Direct addressed bit in internal 8032 DATA SRAM (locations 20h to 2Fh) or in SFR
registers (88h, 90h, 98h, A8h, B0, B8h, C0h, C8h, D0h, D8h, E0h, F0h).
Table 10.
Program branching instruction set (continued)
Mnemonic(1) and use
Description
Length/cycles
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