UPSD3422_V01 datasheet(89/300 Pages) STMICROELECTRONICS

89 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422, UPSD3433, UPSD3434, UPSD3454

MCU bus interface

89/300

Table 50.

BUSCON register bit definition

Bit

Symbol

R/W

Definition

EPFQ

R,W

Enable pre-fetch queue

0 = PFQ is disabled

1 = PFQ is enabled (default)

EBC

R,W

Enable branch cache

0 = BC is disabled

1 = BC is enabled (default)

5:4

WRW[1:0]

R,W

WR Wait, number of MCU_CLK periods for WR write bus

cycle during any MOVX instruction

00b: 4 clock periods

01b: 5 clock periods

10b: 6 clock periods (default)

11b: 7 clock periods

3:2

RDW[1:0]

R,W

RD Wait, number of MCU_CLK periods for RD read bus cycle

during any MOVX instruction

00b: 4 clock periods

01b: 5 clock periods

10b: 6 clock periods (default)

11b: 7 clock periods

1:0

CW[1:0]

R,W

Code Wait, number of MCU_CLK periods for PSEN read bus

cycle during any code byte fetch or during any MOVC code

byte read instruction. Periods will increase with PFQ stall

00b: 3 clock periods - exception, for MOVC instructions this

setting results 4 clock periods

01b: 4 clock periods

10b: 5 clock periods

11b: 6 clock periods (default)

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422 Datasheet(PDF) 89 Page - STMicroelectronics

UPSD3422 Datasheet(HTML) 89 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL