UPSD3422_V01 datasheet(180/300 Pages) STMICROELECTRONICS

180 / 300 page

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Analog-to-digital convertor (ADC)

UPSD3422, UPSD3433, UPSD3434, UPSD3454

180/300

1ADST

ADC start bit

0 = Force to zero

1 = Start ADC, then after one cycle, the bit is cleared to '0.'

0ADSF

ADC Status Bit

0 = ADC conversion is not completed

1 = ADC conversion is completed. The bit can also be cleared with software.

Table 140.

ADCPS register details (SFR 94h, Reset Value 00h)

Bit

Symbol

Function

7:4

–

Reserved

ADCCE

ADC conversion reference clock enable

0 = ADC reference clock is disabled (default)

1 = ADC reference clock is enabled

2:0

ADCPS[2:0]

ADC reference clock prescaler

Only three Prescaler values are allowed:

ADCPS[2:0] = 0, for fOSC frequency 16MHz or less. Resulting ADC clock is

fOSC.

ADCPS[2:0] = 1, for fOSC frequency 32MHz or less. Resulting ADC clock is

fOSC/2.

ADCPS[2:0] = 2, for fOSC frequency 32MHz > 40MHz. Resulting ADC clock

is fOSC/4.

Table 141.

ADAT0 register (SFR 95h, reset value 00h)

Bit

Symbol

Function

7:0

–

Store ADC output, Bit 7 - 0

Table 142.

ADAT1 register (SFR 96h, reset value 00h)

Bit

Symbol

Function

7:2

–

Reserved

1.. 0

–

Store ADC output, Bit 9, 8

Table 139.

ACON register bit definition (continued)

Bit

Symbol

Function

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UPSD3422 Datasheet(PDF) 180 Page - STMicroelectronics

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