L99DZ100G datasheet(94/197 Pages) STMICROELECTRONICS

94 / 197 page

Application information

L99DZ100G, L99DZ100GP

94/197

DS11546 Rev 5

low). If more or less clock pulses are counted within one frame the complete frame is

ignored. This safety function is implemented to avoid an activation of the output stages

by a wrong communication frame.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected IC's is

recommended.



Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go

from high impedance to a low or high level depending on the global error flag (fault

condition). The first rising edge of the CLK input after a high to low transition of the

CSN Pin will transfer the content of the selected status register into the data out shift



Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data

input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change

with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up

to 4 MHz.

4.12

Power supply failure

4.12.1

VS supply failure

VS overvoltage

If the supply voltages VS reaches the overvoltage threshold VSOV:



LIN remains enabled



CAN remains enabled



OUT1 to OUT_14 are turned off (default).

The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN (CR 3) = 0)



Charge pump is disabled (and is switched on automatically in case the supply voltage

recovers to normal operating voltage)



H-bridge gate driver and heater MOSFET gate driver are switched into sink condition



ECV is switched in high impedance state and ECDR is discharged by RECDRDIS (to

ensure the gate of the external MOSFET is discharged => EC mode considered as off)



Recovery of outputs after overvoltage condition is configurable by SPI:

–

VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_OV (SR 2).

–

VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after VS overvoltage

condition has recovered.



The overvoltage bit VS_OV (SR 2) is set and can be cleared with a ‘Read&Clear’

command. The overvoltage bit is reset automatically if VS_LOCK_EN (CR 3) = 0 and

the overvoltage condition has recovered.

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