ATMEGA6450SLASHV datasheet(32/347 Pages) ATMEL

32 / 347 page

ATmega325/3250/645/6450

2570A–AVR–09/04

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that

no glitches occur in the clock system and that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock fre-

quency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided

clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to

determine the state of the prescaler – even if it were readable, and the exact time it

takes to switch from one clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2

before the new clock frequency is active. In this interval, 2 active clock edges are pro-

duced. Here, T1 is the previous clock period, and T2 is the period corresponding to the

new prescaler setting.

Table 13. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0000

0001

0010

0011

0100

0101

0110

0111

128

1000

256

1001

Reserved

1010

Reserved

1011

Reserved

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

ATMEGA6450/V Datasheet(PDF) 32 Page - ATMEL Corporation

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